Related Publications
1) "GLAF: A Visual Programming and Auto-Tuning Framework for Parallel Computing" (ICPP 2015)
* The version available at Try GLAF Online! contains certain differences compared to the version presented in this work. The online version has been adapted to enable a fully client-side workflow (original version was implemented as a server- and client-side).
Pre-print (PDF)    Presentation    IEEE Xplore Link    BibTex ReferenceAbstract:
The past decade's computing revolution has delivered parallel hardware to the masses. However, the ability to exploit its capabilities and ignite scientific breakthrough at a proportionate level remains a challenge due to the lack of parallel programming expertise. Although different solutions have been proposed to facilitate harvesting the seeds of parallel computing, most target seasoned programmers and ignore the special nature of a target audience like domain experts.
This paper addresses the challenge of realizing a programming abstraction and implementing an integrated development framework for this audience. We present GLAF — a gridbased language and auto-parallelizing, auto-tuning framework. Its key elements are its intuitive visual programming interface, which attempts to render expressing and validating an algorithm easier for domain experts, and its ability to automatically generate efficient serial and parallel Fortran and C code, including potentially beneficial code modifications (e.g., with respect to data layout). We find that the above features assist novice programmers to avoid common programming pitfalls and provide fast implementations.
2) "Bridging the FPGA Programmability-Portability Gap via Automatic OpenCL Code Generation and Tuning"* (IEEE ASAP 2016)
* Latest updates presented in this work are not yet included in the Try GLAF Online! version.
Pre-print (PDF)    Presentation    IEEE Xplore Link    BibTex ReferenceAbstract:
Programming FPGAs has been an arduous task that requires extensive knowledge of hardware design languages (HDLs), such as Verilog or VHDL, and low-level hardware details. With OpenCL support for FPGAs, the design, prototyping and implementation of an FPGA is increasingly moving towards a much higher level of abstraction, when compared to the intrinsically low-level nature of HDLs. On the other hand, in the context of traditional (i.e., CPU) software development, OpenCL is still considered to be low-level and complex because the programmer needs to manually expose parallelism in the code. In this work, we present our approach to enhancing FPGA programmability via GLAF, a visual programming framework, to automatically generate synthesizable OpenCL code with an array of FPGA-specific optimizations. We find that our tool facilitates the development process and produces functionally correct and well-performing code on the FPGA for our molecular modeling, gene sequence search, and filtering algorithms.